This invention relates to electronic device fabrication processes and associated apparatus. More specifically, the invention relates to conformal nanolaminate deposition and dry etch processes for forming dielectric layers, particularly in high aspect ratio, narrow width recessed features.
It is often necessary in semiconductor processing to fill a high aspect ratio gap with insulating material. As device dimensions shrink and thermal budgets are reduced, void-free filling of high aspect ratio spaces (e.g., AR>3.0:1) becomes increasingly difficult due to limitations of existing deposition processes. The method currently used for high aspect ratio (AR) gap-fill is deposition of doped or undoped silicon dioxide assisted by high density plasma chemical vapor deposition (HDP CVD), a directional (bottom-up) CVD process. Evolving semiconductor device designs and dramatically reduced feature sizes have resulted in several applications where HDP processes are challenged in filling the high aspect ratio structures (e.g., AR>7:1) using existing technology (see, for example, U.S. Pat. No. 6,030,881 and U.S. Pat. No. 6,846,745). For structures representative of the 65 nm and 45 nm technology nodes, engineering the gap fill process becomes structure dependent, requiring that the process be re-optimized, a task of considerable complexity, every time a new structure needs to be filled.
Accordingly, improved gap fill techniques, particularly for gap fill of small, high aspect ratio structures, are needed.